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                  AXI slave verilog code

                  size:14px;">自己寫的 AXI slaver  verilog code,希望帶給大家一些啟示...

                  Verilog Jpeg Encoder

                  contained. This core has been simulated on many raw images with different quantification and Huffman tables....

                  FFT FFT algorithm based on Verilog

                  size:16px;">該代碼實現128點,16位整型的FFT計算,基于Quartus II 8.0版本,已經過仿真,時序約束和實際驗證,程序功能完全能達到正常情況下的需求,時鐘可達150Mhz。...

                  Histogram equalization FPGA implementation

                  size:16px;">在fpga上實時實現圖像的直方圖均衡化,有效利用fpga芯片的片內資源,不需要添加片外的存儲芯片。本代碼是基于ycbcr處理的,其實只對亮度分量進行直方圖均衡化,之后同步cb,cr顏色分量,避免偏色問題!代碼接口為y...

                  HDMI interface chip (ADV7513) drive, 1080p60,720p60 colour bar test!

                  size:16px;">本工程實現了hdmi芯片的配置和驅動測試,可以選擇性配置為1080P60,720p60,ddrmode等模式,1080p60和720p60格式的視頻圖像現在是主流格式,而ddrmode可以大大節省fpga上寶貴的管腳資源,本工程可選擇性配置為444或422色彩空間...

                  DDR2 controller, Verilog source code

                  Using Verilog prepared of DDR2 controller, achieved has DDR2 of reads and writes function, in Xilinx vietex5 Shang to achieved, achieved has Imaging algorithm in the of data turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,...

                  Booth multiplier in verilog

                  size:14px;">This file describes the code for booth multiplier in verilog. the source code is simulated and verified for better results...

                  Flash controller verilog code

                  This is the verilog code of Samsung K9 series Flash controller, it is complied and verified on FPGA development board, the verification environment is quartusii and modelsim combined platform. You can find the datasheet of K9 flash on the internet. The size of the flash is 1024*32....

                  1024-bit RSA encryption algorithm

                  1) are prime numbers from each other.Finally, calculate the decryption key d use Euclid extended algorithm to meet the requirement ofed = 1(mod(p–1)(q–1 ))i.e.d = e–1 mod((p–1)( q – 1 ))e and n are public key,d is private key...

                  Verilog code for the GPS baseband processing

                  GPS software receiver baseband processing Verilog programs, by spread spectrum demodulation, intermediate frequency data synchronization process converts the raw navigation data...

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