verilog - Free Open Source Codes

FIFO is a First-In-First-Out memory queue with control logic that managesthe read and write operations, generates status flags, and provides optionalhandshake signals for interfacing with the user logic. It is often used tocontrol the flow of data between source and destination. FIFO can beclassifie...

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6 hours ago

by sebastianleong

verilog Verilog

▍verilog matlab IIR digital filter

verilog matlab IIR digital filter, IIR low pass filter, MATLAB and verilog program exactly correspond to IIR low pass filter, MATLAB and verilog program exactly correspond to IIR low pass filter, corresponding to MATLAB and verilog program...

6 hours ago

Verilog Verilog

▍verilog Modified Baugh Wooley 8 x 8 Multiplier

This code is for Modified Baugh Wooley Multiplier with multiplier strength-8 x 8, and written in verilog Gate level or structural port mapping method and test verified with functional simulation from Xilinx and Altera Quartus II...

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274

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12 hours ago

by Pradeep N

verilog Verilog

▍verilog HDL design and development laboratory

The most detailed collection of verilog examples, rapid entry to the master. As an experimental tutorial this tutorial is divided into two parts: the FPGA hardware system based on verilog and advanced interface design experiments. For the beginner can quickly get started. For those who have come int...

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1009

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3 hours ago

by hgq_love_wr

Verilog Verilog

▍verilog implementation of 8 bit ahead carry adder

Application backgroundResource descriptionWith verilog implementation of the 8 carry carry adder, decompression is the word document, the source code in the document, the Modelsim has been verified...

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803

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11 hours ago

by qq:東

Verilog Verilog

▍UART_verilog

UART_verilog,,,,,,UART_verilogUART_verilogUART_verilogUART_verilogUART_verilogUART_verilogUART_verilogUART_verilog...

12 hours ago

Verilog All

▍verilog code for RS232

verilog code for RS232, is divided into three modules, clock generator, sending data, receive data module. Function of the whole project is that your host computer sends data from the serial port, serial port to send the data back to the PC...

9 hours ago

Verilog RS232代碼 All